http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1875507-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823878 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0922 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1207 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 |
| filingDate | 2006-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5ec51cea5cdf0a5040d7a56c03d0c071 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6ca057efe5ad5c8a5281a6d2e2641603 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c7eeb7c5fe0dc5a5fbafb4ecfeae8b77 |
| publicationDate | 2008-01-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-1875507-A2 |
| titleOfInvention | Hybrid crystal orientation cmos structure for adaptive well biasing and for power and performance enhancement |
| abstract | The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs. |
| priorityDate | 2005-04-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 21.