http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1770709-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36f8253f3d0d59bcd9259217d4385d10 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2281 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-83 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-31 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-79 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-832 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0011 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0026 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0007 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02 |
| filingDate | 2005-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_012e98a39ea81cee84f8c5914efa8ba5 |
| publicationDate | 2007-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-1770709-A1 |
| titleOfInvention | Memory device comprising an array of resistive memory cells with bit lines precharging |
| abstract | Memory device comprising an array of resistive memory cells 1, which are arranged in columns and rows, and wherein each resistive memory cell 1 each is connected to a word line 2, to a bit line 3, and to a reference electrode 4. The word lines 2 are assigned to said rows and the bit lines 3 are assigned to said columns. The resistive state of the resistive memory cells 1 corresponds to a logical state thereof, and the memory device further comprises an evaluation device 6, which is coupled to the bit lines 3, for evaluating the resistive state of at least one of the resistive memory cells 1 during a reading operation. The respective resistive memory cell 1 is selected by addressing the word line 2 to which the resistive memory cell 1 is connected. The memory device furthermore comprises a charging device 5, which is coupled to the bit lines 3, and the charging device 5 is capable of charging the bit lines 3 to a pre-determined pre-reading bit line potential before carrying out a reading operation. |
| priorityDate | 2005-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 49.