http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1765725-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c5397fc5ff75ee49a454558b68b36baa |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-81 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-306 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-861 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-045 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0665 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82B3-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B81B7-00 |
| filingDate | 2005-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1ab3f9230c0a76585bf108642e9d8aad http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3738b4c271eee40eb8324e3e471dceec http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1a9ef6e6d039a1b46145bff4e666fc0e |
| publicationDate | 2007-03-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-1765725-A2 |
| titleOfInvention | Nanowire device with (111) vertical sidewalls and method of fabrication |
| abstract | A nano-scale device 10, 20, 30, 60 and method 40, 50, 70 of fabrication provide a nanowire 14, 24, 34, 64 having (111) vertical sidewalls 14a, 22e, 34a, 64a. The nano-scale device includes a semiconductor-on-insulator substrate 12, 22, 32, 62 polished in a [110] direction, the nanowire, and an electrical contact 26, 35 at opposite ends of the nanowire 24, 34. The method 40, 50, 70 includes wet etching 42, 52, 72 a semiconductor layer 12a, 22a, 32a. 62a of the semiconductor-on-insulator substrate to form 44, 54 the nanowire 24, 34 extending between a pair of islands 22f, 32f in the semiconductor layer 22a, 32a. The method 50 further includes depositing 56 an electrically conductive material on the pair of islands to form the electrical contacts 26, 36. A nano-pn diode 60 includes the nanowire 64 as a first nano-electrode, a pn-junction 66 verically stacked on the nanowire 64, and a second nano-electrode 68 on a (110) horizontal planar end of the pn-junction. The nano-pn diode 60 may be fabricated in array of the diodes on the semiconductor-on-insulator substrate 62. |
| priorityDate | 2004-07-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 40.