| abstract |
A storage system controller (302) includes a plurality of media controllers (301), a localnmicroprocessor (306), and a host interface logic (310), operably coupled by a multi-dropnparallel bus. The multi-drop parallel bus (319) includes a control bus (324), a payload datanbus (320), a real-time ready-status (data ready) signaling bus (322) and a generalnmicroprocessor bus (330). Each media controller has a storage media (311) operably couplednthereto. Each media controller includes a parameter storage (404), a media interface circuitn(406), a control data state machine (408), a command sequencer state machine (410), anmedia-side multi-mode transfer state machine (412), a dual-port memory (402), a memoryncontroller (420), and a host-side transfer state machine (430). The host interface logic andnthe media controllers are implemented in one or more Field Programmable Gate Arrays. Thenstorage system architecture allows the microprocessor to simultaneously broadcast ancommand to the media controllers, which have a capability to substantially simultaneouslynbegin exchanging data with the storage media in response to the command. The storagensystem has provision for Redundant Array of Independent Disks, method 0, operation. |