| abstract |
A programmable logic device and associated method is provided withnrepairable regions. In one aspect, general routing interconnect lines are segmentednwithin repairable regions. In another aspect, IO bus lines and associated circuitry arenprovided that accommodate redundancy in a staggered segmented architecture. Innanother aspect, a dedicated routing architecture between particular logic regionsnaccommodates shifting to define and utilize repairable regions. Principles of othernaspects are illustrated and described in the context of several exemplary embodimentsnof aspects of the invention. |