| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1f11ae49f99415a9a8079d77fef6d1b8 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0458
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-24 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 |
| filingDate |
2002-07-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_91b828cba6329c1832e8ff71d8838cea |
| publicationDate |
2003-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-1274094-A2 |
| titleOfInvention |
Bit line decoding scheme and circuit for dual bit memory with a dual bit selection |
| abstract |
A bit line decoder scheme is described that connects data and voltage to anplurality of bit lines of a dual bit flash memory array. The bit lines are connected tona plurality of intermediate data lines by a first decoder unit and the intermediatendata lines are connected to a plurality of data lines of the sense amplifiers by ansecond decoder unit. In one embodiment the voltage is connected to a selectednbit line through a separate decoder unit and in a second embodiment the voltagenis connected through the decoder unit connected to the intermediate data lines. |
| priorityDate |
2001-07-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |