| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_06692db7881d681828270358c02ac430
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c5520dd38cc403678d9f91e0b0ee95fb |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7926
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7881
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate |
2002-06-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c387b1ecadeceb0f51683d2c1b3aa21c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_22984854d6693ae9372e5d0c376c3c32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e67f56e5bc623f44b2a7c25aab9e137f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0744d06fcfacc46db1762a764f51aa22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7b758798a81e03e03638cf4f2b8b8d42 |
| publicationDate |
2003-01-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-1271652-A2 |
| titleOfInvention |
A semiconductor memory and its production process |
| abstract |
A semiconductor memory comprises: a first conductivityntype semiconductor substrate (100) and one or more memory cellsneach constituted of an island-like semiconductor layer (110) havingna recess on a sidewall thereof, a charge storage layer (510) formednto entirely or partially encircle a sidewall of the island-likensemiconductor layer, and a control gate (520) formed on the chargenstorage layer, wherein at least one charge storage layer of said onenor more memory cells is partially situated within the recess formednon the sidewall of the island-like semiconductor layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7816728-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8120095-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2005083782-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7719046-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1869709-A2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7369436-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1869709-A4
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7148538-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7807526-B2 |
| priorityDate |
2001-06-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |