| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30167
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-321
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30087
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30018
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30058 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-315
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-312 |
| filingDate |
2000-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5912d4d8ca00c4b3760bc0ad7970f1b3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6779dc512952244a3f3e5d97009686d5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1e8553e16185e184111c40b0e11431b9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e81aa270e549a85da3d588402a9b6597
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1e5dd80d2e9fe27ff2609ca0d2081b63 |
| publicationDate |
2002-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-1236094-A1 |
| titleOfInvention |
Branch instruction for multithreaded processor |
| abstract |
A parallel hardware-based multithreaded processor (12) is described. The processor (12) includes a general purpose processor that coordinates system functions and a plurality of microengines (22a-22f) that support multiple hardware threads or contexts. The processor (12) also includes a memory control system (16) that has a first memory controller (26a) that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller (26b) that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed. |
| priorityDate |
1999-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |