| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30058
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30087
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30018
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3851
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-321
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30167 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-315
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-312
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-32 |
| filingDate |
2000-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1e8553e16185e184111c40b0e11431b9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5912d4d8ca00c4b3760bc0ad7970f1b3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e81aa270e549a85da3d588402a9b6597
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6779dc512952244a3f3e5d97009686d5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1e5dd80d2e9fe27ff2609ca0d2081b63 |
| publicationDate |
2002-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-1236088-A1 |
| titleOfInvention |
Register set used in multithreaded parallel processor architecture |
| abstract |
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD_3 ... THREAD_0). The processor maintains execution threads (THREAD_3 ... THREAD_0). The execution threads (THREAD_3 ... THREAD_0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD_3 ... THREAD_0). |
| priorityDate |
1999-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |