http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1216530-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_26e69ef7b7bc98bfe778e419ccd664c9 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04B1-7073 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04W56-005 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04B7-2678 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04B1-7073 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04J13-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L1-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04B7-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04J3-06 |
| filingDate | 2000-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2004-01-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c38beba366ad905691b6d9c3e4e54eac http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_571e8c8b01bb3723d3a66c44c3e69670 |
| publicationDate | 2004-01-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-1216530-B1 |
| titleOfInvention | Apparatus and method for time-aligning data frames of a plurality of channels in a telecommunication system |
| abstract | In a telecommunication system where data frames of a plurality of channels (CH1, CH2, ... CHn) arrive with respective different time-offsets with respect to a common synchronization clock (WR, R/W, RD, T) of an internal frame structure of a decoder (DEC), three frame memories (RAM1, RAM2, RAM3) are used for performing a time-alignment of the data frames. The data frames are respectively written to two frame memories (RAM1, RAM2) having a read state and a reading of one frame memory (RAM3) is performed beginning with the occurrence of the common synchronization clock (T). A cyclic switching of the read/write state of the frame memories (RAM1, RAM2, RAM3) is performed, such that always two frame memories (RAM1, RAM2) are in a write-state (WR) and one frame memory (RAM3) is is in a read-state (RD). The frame memory (RAM3) in the read-state is read out synchronized to the common synchronization clock. |
| priorityDate | 1999-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 47.