| abstract |
A semiconductor memory device having anplurality of word lines (WLs), a plurality of bit linesn(BLs), and memory cells (MCs) disposed at intersectionsnof the word lines and bit lines. A decoder circuitn(901; 912, 914) selects one memory cell according to annaddress signal in a normal decoding function, andncarries out a full selection operation or annonselection operation of the word lines or bit linesnin a test function. The decoder circuit comprises annoutput row or a decoding row connected to a first powernsource (904) and a second power source (905), the firstnpower source supplying a high voltage (Vcc), and thensecond power source supplying a reference voltage (Vss)nor the high voltage in response to a control signaln(AH, AL). |