http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1129488-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b7317808024e524eea40a6c5a5ad6a22 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66757 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42384 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66765 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-458 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4908 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G03F7-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-786 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-45 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1368 |
| filingDate | 2000-08-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a8ed3b43ea93492e1bba8cdeae71c059 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8c48e22e1da4e1fbbd519fed4d471c36 |
| publicationDate | 2001-09-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-1129488-A1 |
| titleOfInvention | Thin-film transistors and method for producing the same |
| abstract | A method of forming a thin film transistor comprises providing first electrode layers (42) over a transparent substrate (40), the first electrode layers comprising a lower transparent layer (42a), and an upper opaque layer (42b). The first electrode layers are patterned to define a first electrode pattern in which an edge region of the transparent layer (42a) extends beyond an edge region of the opaque layer (42b). A transistor body region comprising a semiconductor layer (16) defining the channel area of the transistor and a gate insulator layer (18) is provided over the first electrode pattern (42). A transparent second electrode layer (46) is also provided. A negative resist (70) is exposed through the substrate (40), with regions of the negative resist layer (70) shadowed by the opaque layer (42b) of the first electrode pattern (42) remaining unexposed. These regions and the underlying second electrode layer (46) are removed to define a second electrode pattern which is substantially aligned with the opaque layer (42b) of the first electrode pattern (42). The method can be used for top or bottom gate TFTs and provides a self aligned gate structure with overlap between the source/drain and the gate, so that no additional processing of the semiconductor body is required. |
| priorityDate | 1999-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.