http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1121656-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bf6d86a7f19054f55453055ea0e2ff25 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-30 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-50 |
| filingDate | 1999-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7fc6ae83a234bfd03f70bfb9b33325c0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f548606b497e4f3ccf595b6eebd64be3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0f25234091a4efd1c431fd837c627f99 |
| publicationDate | 2001-08-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-1121656-A2 |
| titleOfInvention | Method and apparatus for managing the configuration and functionality of a semiconductor design |
| abstract | A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating 'makefiles' for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed. |
| priorityDate | 1998-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 21.