http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1102312-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2c78d80e9d323ad7c79518c80e0b8d16 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311 |
| filingDate | 2000-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0ce7d8fb2556f4b15e790ba5ff4598ac http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34f992243be21ab7ec9083ea267748c7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_72d78193d20fce8d231ea827626be3c2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_092423b0d0d2502c291f3f2a7ec265ba http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9b697ad0642eab13f0b44d9583934054 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7878e5961d9b1dec2267590dc241db18 |
| publicationDate | 2001-05-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-1102312-A2 |
| titleOfInvention | Method for selective oxide etching in pre-metal deposition |
| abstract | A method for completely removing dielectric layers formed selectively uponna substrate employed within a microelectronics fabrication from regions whereinnclosely spaced structures such as self-aligned metal silicide (or salicide) electricalncontacts may be fabricated, with improved properties and with attenuatedndegradation. There is first provided a substrate with employed within anmicroelectronics fabrication having formed thereon patterned microelectronicsnlayers with closely spaced features. There is then formed a salicide block layernemploying silicon oxide dielectric material which may be selectively doped. Therenis then formed over the substrate a patterned photoresist etch mask layer. Therenis then etched the pattern of the patterned photoresist etch mask layer employingndry plasma reactive ion etching. An anhydrous etching environment is thennemployed to completely remove the silicon oxide dielectric salicide block layernwith attenuated degradation of the microelectronics fabrication. |
| priorityDate | 1999-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 57.