| abstract |
Each chip includes, in addition to a core logic, anregister such as a BSR. A TAPC for controlling thenregister is provided only on a chip of the first stage,nand an test commands/data output and input signal linesnfor the boundary scan test are connected to each othernvia wire to form a loop. Other signal lines used in thentest are distributed from an output signal line of thenchip of the first stage. As a result, the test needs tonbe carried out only once with a smaller number of pinsnand the number of steps and area can be reduced in chipsnnot provided with TAPC. With this arrangement, in anstacked device in which a plurality of chips arenintegrally sealed, the boundary scan test only needs tonbe carried out once with a smaller number of pins. |