http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-1070294-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8f6fd8a92f55dca0f111bd7c5858ae83 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3887 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3885 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-8023 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30167 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30145 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-80 |
| filingDate | 1999-04-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52eaf238e3e5703ad792441c2b194bfb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f135afff6685cb2e9b8ff2d70eaaba05 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_47effee54376f506261d94b77c02db55 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d4973c8db7b68080edb49664edd3b4bc http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0f9696dfcc2076d4a454c693ee186f3b |
| publicationDate | 2001-01-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-1070294-A2 |
| titleOfInvention | Mesh connected computer |
| abstract | An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array. In another aspect, a programmer references images via pointers to image descriptors that include the actual addresses of various bits of multi-bit data. Other features facilitate and speed up the movement of data into and out of the apparatus. 'Hit' detection and histogram logic are also included. |
| priorityDate | 1998-04-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.