| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c33df106dcb6edbf2785f8cbe55d5d00 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-351
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2200-1612
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01005
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01082
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05572
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01078
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01322
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05647
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-02377
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01051
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01049
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05548
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-02381
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01057
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-131
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13024
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0001
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01013
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01023
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0231
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13007
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-01029
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05124
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-0235
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13017
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05166
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13099
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-06131
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-05155
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-10 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3114
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-1601 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-16 |
| filingDate |
1998-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7925f0c75d270da0c9b6754ae5c39824
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_add29e6b92ed67a51bb7ff81bc82cefc |
| publicationDate |
2001-11-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-1036414-A4 |
| titleOfInvention |
CHIP-SCALE INTEGRATED CIRCUIT BOX USING LARGE DUCTILE WELDING GLOBULES |
| abstract |
A chip scale package design (8) for a flip chip integrated circuit (10) includes a redistribution metal layer upon the upper surface of a semiconductor wafer (14) for simultaneaously forming solder bump pads (26) as well as the metal redistribution traces (30) that electrically couple such solder bump pads with the condutive bond pads (18) of the underlying integrated circuit (10). A patterned passivation layer (32) is applied over the redistribution metal layer (30). Relatively large, ductile solder balls (28) are placed on the solder bump pads (26) for mounting the chip scale package (8) to a circuit board or other substrate without the need for an underfill material. The back side (16) of the semiconductor wafer can be protected by a coating (34) for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed. |
| priorityDate |
1997-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |