http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0878836-A2

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31055
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302
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filingDate 1998-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2eb646eed8ad1693c91147aaa648d0dd
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publicationDate 1998-11-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber EP-0878836-A2
titleOfInvention Planarising a semiconductor substrate
abstract A method for planarising a substrate 10, such as ansemiconductor substrate, having an uneven topography usesndifferent etch rates of insulating layers. First 14 andnsecond 16 insulating layers are formed on an elevatednregion and a recessed region. Portions of the secondninsulating layer at an interface between the elevatednregion and the recessed region are removed, to isolate anportion of the second insulating layer within thenrecessed region from a portion of second insulating layernoverlying the elevated region. A third insulating layern18 is formed on the resultant surface, and is partiallynremoved from its upper surface until a part of thenportion of second insulating layer overlying the elevatednregion is exposed. The portion of second insulating layernoverlying the elevated region is removed, causing lift-offnof corresponding portions 18a of the third insulatingnlayer.
priorityDate 1997-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 26.