http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0860782-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f4964ada6006caac1715f7f32f5df380 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L69-324 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-104 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-2215 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L29-08 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-267 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-38 |
| filingDate | 1998-02-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2003-05-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_435d14e8432d1d41234b379bd82f05ea http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4ea4f561463bf791e8921964520e08e7 |
| publicationDate | 2003-05-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0860782-B1 |
| titleOfInvention | Method of initialisation of a serial link between two integrated circuits having a parallel/serial port and device using such method |
| abstract | The method uses an input-output port between a parallel bus and a serial link. The port uses two clocks of different frequency, a first being of high frequency for the serial link called the transmission clock (CKT/CKR), and a second of lower frequency for the signals arriving from the parallel bus called the system clock (CKS). The method involves a first step of re-initialisation of the port with isolation of the reception clock; a second step of the re-initialisation of the transmission clock logic (CKT); and a third and final step of returning to zero the serial link between the two ports. Re-initialisation includes a stage in which the microprocessor associated with the port to be re-initialised transmits a series of neutral messages which allows a reception delay line to extract a reception clock signal (CKR) then transmit a calibration signal (CAL) indicating that the reception clock is calibrated. |
| priorityDate | 1997-02-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 68.