| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9fc0a00eab3a757e8324b1e887d7ba97 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-0209
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-015
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-068
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-4611
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-429 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3735
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3737
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2863
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-4641
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R1-07314 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-42 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-46
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R1-073
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-373 |
| filingDate |
1996-02-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a3e5ad7715767f0a2ab9a4aff27ca537
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2fc74a96227438fe578cefeb187bdb03
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_70e406d511ca8976cc77a6c048e3114e |
| publicationDate |
1996-10-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-0737027-A2 |
| titleOfInvention |
Integrated circuit testing board having constrained thermal expansion characteristics |
| abstract |
A board (10) for testing an integrated circuit disposed on a semiconductor wafer. The board contains a plurality of substantially parallel signal layers (14) and power planes (16) that are supported and electrically isolated by a dielectric material (12). One or more constraint layers (18,20) are disposed in the dielectric material, and the constraint layers have a coefficient of thermal expansion of about 1-6 ppm/ o C. In a preferred embodiment, the dielectric material is a fluoropolymer with a ceramic or silica filler, and the constraint layers are an iron-nickel alloy of about 30-40 percent nickel by weight. The board has thermal expansion characteristics substantially similar to silicon to ensure good contact to a silicon wafer during burn-in testing. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0891125-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5953210-A |
| priorityDate |
1995-03-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |