http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0610259-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_67cf3a1336f0e8b09c13c7c4d2535e7e |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2207-3884 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2207-4812 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2207-4816 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-501 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-507 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-5338 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-09448 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-0944 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-527 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-507 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-533 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-53 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-52 |
| filingDate | 1992-10-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_97091987288a1b325ddc92acc268bae5 |
| publicationDate | 1994-08-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0610259-A1 |
| titleOfInvention | 1 BIT ADDER AND MULTIPLIER INCLUDING IT. |
| abstract | Video applications, for example, require fast high definition multipliers, but higher definition results in an increase in the number of partial products to be calculated internally. The Booth-McSorley algorithm can be used to reduce the required number of these partial products. This algorithm can be associated with a diagonal propagation of the carry over between one of the partial products and another, which allows simultaneous calculation of all the sums of the same row. Despite this, the multiplication time thus obtained is still not short enough. An almost entirely CMOS design multiplier constructed using 1.2mum BICMOS technology has been provided with its multiplication time being 9ns when the supply voltage is 5 volts. The multiplication time was minimized by combining the following techniques with one another: the use of the Booth-McSorley algorithm in order to reduce the number of partial products; the diagonal propagation of the carry over between one of the partial products and another, which allows the simultaneous calculation of all the sums of the same row; using the carry selection approach in the last 14-bit adder and in the first two adders of the intermediate rows; and the use of these full and fast logic 1-bit adders with complementary ballast transistors. |
| priorityDate | 1991-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.