http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0602607-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5547f741b25666fc4ae5195cf71a979b |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76819 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-304 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 1993-12-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eeeebf1c8c90fd2a4adfcee4c63bc3d2 |
| publicationDate | 1994-06-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0602607-A1 |
| titleOfInvention | Method for fabricating multi-level interconnection structure for semiconductor device |
| abstract | A method for fabricating a semiconductor device includes the steps of forming an interconnect metal film (33) on an insulating layer (32) and forming, on a surface of the interconnect metal film, a first insulating film (34) formed of P-SiN. The first insulating film (34) and the interconnect metal film (33) are simultaneously patterned to form a lower interconnect (33A). On the resulting surface, a second insulating film (35) having a polishing rate higher than that of the first insulating film (34) is formed. The entire surface of the second insulating film (35) is flattened by a chemical mechanical polishing process using the first insulating film (34) as a stopper. Then, on the resulting surface, a third insulating film (36) is formed. According to one embodiment, the first insulating film (34) used as the stopper remains on the lower interconnect (33A) but not between adjacent interconnects and, according to another embodiment, such film (34) is completely removed by etching. Thus, an increase in the capacitance between the interconnects is prevented and any stress migration therein is suppressed. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5795495-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6825132-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-1088257-C http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6690084-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6831015-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0961315-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6917110-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6794283-B2 |
| priorityDate | 1992-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.