http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0577813-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_05060720d78cc9178696073231d89834 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-17381 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-10 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-173 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10 |
| filingDate | 1993-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1998-03-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7c86e0782fd88ab178b65935edee2469 |
| publicationDate | 1998-03-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0577813-B1 |
| titleOfInvention | Databus parity and high speed normalization circuit for a massively parallel processing system |
| abstract | A processing array including a plurality of processing elements; and an interconnection network connected to all of the processing elements, wherein each of the processing elements includes a parity generating circuit for generating a parity bit for a first data message that is transmitted by that processing element to another processing element; and a separate parity circuit for checking parity of a second data message as it is received by that processing element over the interconnection network. Each processing element includes a shift register capable of storing an N-bit number; shifter control circuitry connected to the shift register for causing the shift register to shift the N-bit number in a preselected direction m bits at a time (m>1, N>=m), and detection circuitry connected to the shift register, the detection circuitry monitoring the m most significant bits of data stored in the shift register and asserting a non-zero detect signal when any of the m most significant bits is a non-zero bit, wherein the shifter conttrol circuitry receives the asserted non-zero detect signal and responds to it by disabling shifting. |
| priorityDate | 1992-01-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 39.