| abstract |
The invention relates to a fuzzy logic controller which consists of a fuzzification circuit (FUZ), a control decoder (RDEC), a control evaluation circuit (RA), an inference circuit (INF), a defuzzification circuit (DFUZ) and a sequence control (CTRL), the control decoder Numbers (NA) for linguistic values of the output variables can be formed together with selection signals (SM) to determine the input variables affected by the respective rule and, in addition to the values (ME) of the membership functions for the linguistic values of the input variables, can be fed to the rule evaluation circuit and in this for everyone linguistic value of the output variables a weighting signal (G) can be generated. The advantages that can be achieved with the invention are in particular the high processing speed, the small chip area requirement, the variable control format and the choice of different operating modes in the control evaluation circuit, in the inference circuit and in the defuzzification circuit. |