| abstract |
Video luminance data from a video signal is selectably compressed and expanded in a first signal path including a first line memory (356). A second line memory (358) in a parallel signal path processes video chrominance data from the video signal. A control circuit (320) generates respective timing signals for writing data into the line memories and for reading data from the line memories. A timing delay circuit (337) for the control means, has video compression and expansion modes of operation. During the compression mode, reading of the second line memory is delayed relative to writing of the second line memory. During said expansion mode, writing of the first line memory is delayed relative to writing of the second line memory or reading of the second line memory is delayed relative to writing of the second line memory. The duration of the timing delays can be selected from a range of values. The line memories are first in first out (FIFO) devices having independently enabled write and read ports. |