| abstract |
Peripheral mass memory subsystem (PSS₁, PSS₂) belonging to a computer system comprising at least one central host (H₁, H₂, H₃, H₄) comprising two control units (UC₁, UC₂) of at least one memory ground (BMD₁, BMD₂, ...), with independent electrical power supplies (ALIM₁, ALIM₂, BAT₁, BAT₂) and each having a plurality of structural elements (hardware + firmware) (PR₁ - PR₂, DE₁ - DE₂, CA₁ - CA₂ , HA₁ - HA₂, DA₁ - DA₂) connected to a first and / or a second parallel type bus (B₁, B₂).n n n According to the invention, the subsystem is characterized in that it comprises a firmware architecture (AML) executing the commands of the host and preventing it from changes in the state of the mass memory, formed of a plurality functional firmware subsets (B, H, D, C, S) each of which is specific to each structural element of each control unit and implemented in the material structure thereof. |