http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0443811-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5547f741b25666fc4ae5195cf71a979b |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-15 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11 |
| filingDate | 1991-02-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_46fd4dbf2efc12eb53d78fe02b915cd9 |
| publicationDate | 1991-08-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0443811-A2 |
| titleOfInvention | Semiconductor memory device |
| abstract | By provided a dummy region, having a shape similar to and being formed in the same process as, the active regions having transistors that constitute memory cells formed therein, between two transistors, the spacing between the active region and the dummy region is made to be equal to the spacing between other transistors. n By reducing the nonuniformity in the gate width of the transistors within the memory cell array regions with the above arrangement, it is possible to prevent the reduction of the transistor performance, and to prevent a performance reduction and the generation of malfunctions due to a delay in the data output time of the semiconductor memory device. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0550177-A1 |
| priorityDate | 1990-02-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 16.