http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0365492-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_040ec81c891acc3f3186f56cb99cf161 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-978 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-911 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76819 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28525 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-285 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 |
| filingDate | 1989-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ef53ba6f5c68f457e7e473a9b6c2601b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9580406597f2243d271144d374872016 |
| publicationDate | 1990-04-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0365492-A2 |
| titleOfInvention | Process for forming self-aligned, metal-semiconductor contacts in integrated misfet structures |
| abstract | A process for forming self-aligned metal-semiconductor contacts in integrated MISFET devices determining during a phase of the fabrication the presence on the surface of a wafer of parallel gate lines of polycrystalline silicon provided with lateral "spacers", is founded on the formation of a dielectric oxide layer of a differentiated thickness, having a reduced thickness on the bottom of the valley between two adjacent gate lines wherein the contacts must be formed. The method comprises conformably depositing a first layer of dielectric silicon oxide, a second layer of precursor polycrystalline silicon and a third layer of nitride, followed by depositing a layer of planarization SOG. By blanket etching the SOG layer and the nitride layer, the crests of the precursor polycrystalline silicon layer are exposed. A residual layer of nitride is left inside the valley between adjacent gate lines. The precursor layer of polycrystalline silicon is thermally converted in the areas unmasked by the residual nitride into a dielectric silicon oxide and the removal from the bottom of valleys of the residual nitride and of the residual precursor polycrystalline silicon leaves the front of the wafer covered by a dielectric layer having the desired differentiated thickness, i.e. thinner (corresponding to the thickness of the first conformably deposited oxide layer) on the bottom of valleys between gate lines. By means of a noncritical mask the "length" of the self-aligned contacts is defined and the layer of dielectric is etched until exposing the semiconductor in contact areas along the bottom of the valleys between two adjacent parallel gate lines. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5240872-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/FR-2672429-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8686002-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-4113962-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0528691-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5229325-A |
| priorityDate | 1988-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 34.