| abstract |
A method of interconnecting metal layers in integrated circuits separated by an intermediate dielectric layer by forming first (12,14) and pillar (16,18) layers of metal, etching the pillar layer to form a pillar of electrically conducting material and etching the first level (12,14) to form the first level lead having at least two sides vertically aligned with the pillar (16,18). A layer of dielectric (36) is applied to cover the pillar and first level lead. a layer of photoresist is deposited over the dielectric with a spin on technique to form a planar surface. The dielectric and photoresist are etched back with an equal etch rate until top portion of the pillar is exposed. A second level lead (42,44) is formed atop the pillar (16,18) and planar top surface of the dielectric. |