| abstract |
Random access memory unit with several test modes, built in integrated circuit and without specific input / output pins to define and control the passage in test mode. This unit is provided with means (1) for detecting whether a predefined logic signal sequence, not contained in a set of normally used sequences, but whose voltages are nevertheless included in the range of voltages specified for such signals, is supplied to certain inputs (CE, WE, A0), and to put the unit in test mode when such a sequence has been detected. To define the nature of the test to be carried out, terminals (A1-A8) of the address input of the unit are connected to a test mode decoding circuit (2), in which the data applied to said terminals d 'inputs are used as data defining the nature of the test to be performed. |