http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0313230-A2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_713f9c5df3235e3e1f249d565b5cf2b4 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318538 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3185 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-04 |
| filingDate | 1988-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dca1ae5fb65386e7417eaa38179ffee6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8e5ef5eb3e47b09cc5404206f48e6ab3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8662777709d6e06834b3c531c818a937 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_82feca935cc743294f44a7f78a36b59a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4a5c071467e4ca2f95f9ee02b961455b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_da981067b729f360bc1b2e4cd22a6146 |
| publicationDate | 1989-04-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0313230-A2 |
| titleOfInvention | VLSI chip with test circuitry |
| abstract | A VLSI chip has a core logic area surrounded by a peripheral zone including a plurality of 1/0 cells (10) through which nearly all signals between the pins and the core logic (CLI, CLO) pass. Each cell has an input buffer (IB) and an output buffer (OB) through which signals pass respectively from pin to core logic and vice versa, and a control register controlling the operation of the I/O cells. Two shift registers, an input register and an output register, are formed by flip-flops also included in the I/O cells and connected to the buffers, core logic, and pins, and to test data in and out registers and pins. Some of the I/O cells may be dummy cells forming part of the input and/or output registers but not having pins. Timing circuitry (MS1, MS2; 52, 53) provides early signals (TST EARLY, TCE EARLY) to set up predetermined flip-flops prior to their receiving clocked signals (TST COPY, TCE COPY), and for separating a system clock input (CLKO) as a first clock signal (CLK1) to the control circuitry and a second clock signal (CLK2) to the input and output registers to allow the control register to operate without clocking the input or output registers. |
| priorityDate | 1987-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 43.