http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0307794-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_09d41c9b3057713329370d74ce8b35bb |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0673 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0601 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-06 |
| filingDate | 1988-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e56fd4ca577edf1e2c5e63da32106bcd http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_894cc936f2a89049c639f61f3df41202 |
| publicationDate | 1989-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0307794-A1 |
| titleOfInvention | ESDI interface control circuit |
| abstract | ESDI interface control circuit wherein a shift register is parallel loaded with a 17 bit binary code and with a control information comprising two bits of opposite level, loaded in the head cells of the register, the first bit having a control function, the second having a separation function from the 17 bits binary code, the parallel loading being performed by a load command which also sets a control flip flop and wherein a timing circuit, triggered by command, manages in continuous mode the interlocked interface dialogue, as long as the control flip flop is set, and causes the register to shift its contents so as to serially unload the binary code on the interface and to serially load the register with the logic level of the control bit, until, at binary code transferred, the control bit level present at a predetermined number of register outputs is inverted, reintroduced in the first register cell and causes the control flip flop reset and the dialogue halting. n If the binary code transmission has to be followed by the reception of a binary code, the timing unit is held active and the binary code is serially loaded in the register until the control bit, with inverted logic level, appears at a predetermined output of the register and stops the dialogue, the binary code serially loaded in the register being then available for parallel read out. |
| priorityDate | 1987-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.