http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0282578-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3a62c92e56568bd104089aac22ca487b |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y04S40-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02E60-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02J13-00006 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R19-16528 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R19-165 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04M19-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02J13-00 |
| filingDate | 1987-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1adf4458b64ff2a6d889f2c6ce0f3b0e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_05f7a391ff7df3092803434dd9968cd5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c1291805cd9367583d440980dd4e191c |
| publicationDate | 1988-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0282578-A1 |
| titleOfInvention | Quad exchange power controller |
| abstract | A power control unit making it possible to separately supply a regulated power source to a plurality of “S” lines (S0, S1, S2, S3) and to check on these lines the condition of lines so that each line '' S '' is independently controlled, has an analog part (Vs, VCC, GND) to deliver power independently to each of these '' S '' lines and to detect on them the state conditions of line. The power control unit also includes a microprocessor interface part (14) for communicating with the microprocessor (11) and for controlling the analog part. The latter consists of a plurality of output drive circuits (26) making it possible to individually supply power to the plurality of “S” lines and to the line state detector circuits (24) intended to detect the line state conditions on lines "S" in order to provide a set of logic state signals for each of these lines. The microprocessor interface part comprises an address register (18) making it possible to store a plurality of addresses corresponding to the line state conditions to be checked on the "S" lines. Decoders / multiplexers are provided to select a particular condition among the line condition conditions in response to the addresses, so that the same line condition condition for all "S" lines is readable simultaneously by the microprocessor . A data register (20) receives control signals emanating from the microprocessor as soon as the latter read the line condition conditions, so as to independently de-energize each of the output drive circuits to control the power towards the '' S '' lines. |
| priorityDate | 1986-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.