| abstract |
Arbitration circuit for common bus access granting where the asynchronous access requests are latched in a register (16) with the raising edge of a periodical square wave timing signal, and from there transferred to a logical priority network (17), implemented with a programmable logic array, comprising: n -an arbitration logic (23, 24, 25) disabled in the half period immediately following the raising edge of the timing signal and enabled in the other half period, so as to permit the register (16) to assume a stable state before the arbitration logic is enabled and n -a holding logic (34, 26, 35, 27, 36, 28) for holding the bus access grant signals (CPUG, DMAG, IMDCG) present in output of the arbitration logic also in the half periods in which the arbitration logic is disabled, for the whole time interval required by the communication protocol. |