| abstract |
The MOS field-effect transistor structure according to the invention has single-crystal, doped silicon regions (4) generated by selective epitaxy between the gate electrode (3) and field oxide regions (2), which at the same time act as a diffusion source for the generation of the source / drain zones (6) Substrate (1), and also serve as connection areas for the source / drain connections (7) made of silicide. This connection technology produces particularly planar structures with a high integration density, which are characterized by reduced drain field strength, low series resistances and low risk of substrate short-circuit. The methods for realizing this structure in CMOS circuits are simple to carry out. The invention is applicable to all NMOS, PMOS and CMOS circuits. |