http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0246355-A3
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R35-007 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-05 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R23-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01N35-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R35-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R29-02 |
| filingDate | 1986-11-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 1990-05-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0246355-A3 |
| titleOfInvention | Error and calibration pulse generator |
| abstract | An electronic circuit for selectively ngenerating two output pulses that differ in duration nby a predetermined amount has a clock terminal for nreceiving clock transitions at precisely determined nintervals and comprises first and second sequential nlogic devices (12, 14), a combinational logic device (18) and a nnetwork that couples the clock terminal of the cirncuit to the sequential logic devices and also couples nthe second sequential logic device to the combinantional logic device. The first and second sequenntial logic devices each have a data input terminal (D), na clock input terminal (CLK) and an output terminal (Q), and neach has a first state in which the output terminal nis at one of two binary logic levels and a second nstate in which the output terminal is at the other nof the two binary logic levels. The combinational nlogic device has a first input terminal coupled to nthe output terminal of the first sequential logic ndevice, a second input terminal coupled to the outnput terminal of the second sequential logic device, nand an output terminal at which the desired two noutput pulses are provided. The coupling network nhas first and second separately selectable states nsuch that in the first state of the coupling network na change in the state of the first sequential logic ndevice (12) brings about a change in the state of the nsecond sequential logic device (14) after a first predentermined number of clock transitions, whereas in the nsecond state of the coupling network a change in the nstate of the first sequential logic device (12) brings nabout a change in the state of the second sequential nlogic device (14) after a second predetermined number of nclock transitions, the second number being different nfrom the first number. |
| priorityDate | 1986-05-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID6433 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID226397242 |
Total number of triples: 15.