| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c8e6a13e4ae501eb40decf5732cf09c6 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-18 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-12 |
| filingDate |
1986-04-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd7283ed28b8e1462afaeb6922da3fe2 |
| publicationDate |
1987-04-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-0217937-A1 |
| titleOfInvention |
MEMORY CONTROL CIRCUIT ALLOWING A MICROCOMPUTER SYSTEM TO USE STATIC AND DYNAMIC SELECTIVE ACCESS MEMORIES. |
| abstract |
Control of access to the memory of a microcomputer system, compatible with both dynamic and static memories. A trigger circuit (12) is responsive to read / write enable and address latch control signals from a microprocessor (10), and outputs an enable signal used (at 13) to generate a signal. chip validation compatible with the synchronization and control required by both dynamic and static memories. |
| priorityDate |
1985-04-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |