http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0204768-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76801 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76826 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3213 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 1985-11-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1989-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 1989-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0204768-B1 |
| titleOfInvention | Process for fabricating multi-level-metal integrated circuits at high yields |
| abstract | Inter-layer electrical shorting between layers of conductors of an integrated circuit caused by "hillocks" (20, 22) in the bottom layer (18) is prevented by the use of a double layer photoresist coatings (30, 38) atop the insulating dielectric layer (24) that separates the metal layers (18, 46). The double layer photoresist insures that irregularities in the insulating dielectric layer (24) caused by hillocks (20, 22) in the underlying insulating dielectric layer (24) do not cause a break in the photoresist and a subsequent undesired etching of a spurious "via" through the insulating dielectric layer (24). |
| priorityDate | 1984-12-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 19.