| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3d561728011a96ba60d3a77bc7a12ae0 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-45124
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-45144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-19107
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15184
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-10253
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-85203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-85205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-49175
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48472 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5383
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5382 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-538
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-92
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10 |
| filingDate |
1985-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e7710b51ba86141cb64c6bba32a2fa25
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_15cb17853288d5577f600c962543bcbb |
| publicationDate |
1988-02-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
EP-0173733-A4 |
| titleOfInvention |
Capacitive device. |
| abstract |
Wafer substrate for intergrated circuits (1) which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal (19, 20) thus providing two principal levels of interconnection. A programmable amorphous silicon insulation layer (21) is placed between the metal layers. There are sheet lower metal layers with an insulator which permit power distribution across the wafer. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layers or layers, respectively. Pedestals are provided for bonding. Systems can be formed by interconnection discrete die formed on the wafer or by connection thereto, with hybrid circuits being disclosed. The method of manufacture of the wafer, a capacitive device and an antifuse are disclosed. |
| priorityDate |
1984-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |