http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0138964-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-106 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1056 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-88 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-10 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-406 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-34 |
| filingDate | 1984-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1990-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 1990-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0138964-B1 |
| titleOfInvention | Apparatus for controlling access to a memory |
| abstract | A computer system having a central processing unit, a dynamic memory controller, an error detection and correction network and a dynamic memory for storing data that are subject to being refreshed and to data bit errors. The dynamic memory controller has a refresh mode for controlling access to the memory only to refresh the data, a refresh with error detection and correction mode, for controlling access to the memory to merge or simultaneous refresh a row of data while detecting and correcting data bit errors, and a read/write mode for controlling access to the memory in response to CPU requests for a read/write memory operation. |
| priorityDate | 1983-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419578835 |
Total number of triples: 17.