http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0101791-A3
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-24227 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15153 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-049 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-09745 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-09701 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T428-12396 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-4608 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-10674 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-4644 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-185 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-0203 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-142 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-538 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-46 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K1-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-538 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K1-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-14 |
| filingDate | 1983-04-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 1986-10-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0101791-A3 |
| titleOfInvention | Multi-layer circuitry |
| abstract | Multi-layer circuitry 10 incorporating electronic elements n12-16 is disclosed. The circuitry comprises a plurality of nlayers including a metal or alloy substrate 24 formed with a nrecess 26 on one surface 28. An electronic element 12 is npositioned within the recess and a second electronic element n14 is positioned on the surface 28. Also, a first dielectric nmaterial layer 30 is disposed on the surface 28. Further, a first nlayered conductive circuit pattern 32 overlies the first ndielectric material layer 30 so as to provide circuitry over a nsubstantial portion of the substrate 24. The first circuit npattern is electrically connected to the first electronic elenment. The first circuit pattern also has a cavity 36 therein for nreceiving the second electronic element 14. A second layered nconductive pattern 38 overlies at least a portion of the first nlayered conductive circuit pattern 32 and the second electronnic element 14 and is electrically connected to the second nelectronic element. A second dielectric material layer 40 is ndisposed between the first and second layered conductive ncircuit patterns 32 and 38 so that these circuit patterns are nbonded to and isolated from each other. |
| priorityDate | 1982-08-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.