| abstract |
An improved semiconductor device having a diffused region of reduced length and an improved method of fabricating such a semiconductor device are disclosed. The semiconductor device may be a MOSFET or an IGR, by way of example. In a form of the method for fabricating a MOSFET, an N + SOURCE (66) is diffused into a P BASE (56) through a window of a diffusion mask. An anisotropic or directional etchant is applied to the N + SOURCE through the same window. The etchant removes most of the N + SOURCE, but allows shoulders (72) thereof to remain intact. These shoulders, which form the completed N + SOURCE regions, are of reduced length, greatly reducing the risk of turn-on of a parasitic bipolar transistor in the MOSFET. The risk of turn-on of a parasitic bipolar transistor in an IGR is similarly reduced, when the IGR is fabricated by the improved method. |