http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0066020-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N5-33 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14875 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14856 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N25-711 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04N5-33 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-148 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04N5-372 |
| filingDate | 1981-06-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_80a9dcd8843c919784e9cd8cd0e9340a |
| publicationDate | 1982-12-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0066020-A1 |
| titleOfInvention | Infrared energy detector system utilizing a charge transfer device sensor |
| abstract | A scanning type infrared imaging system comprising a lens system, a scanner, an infrared sensing matrix (16) and a signal processor. Said infrared sensing matrix comprises an array of charge transfer device elements (24) arranged in rows and columns. Each element has four electrodes for receiving phase pulses. The phase 3 and phase 1 electrodes are for transfer gates and the phase 2 and phase 4 electrodes are for charge storage wells. The pulses applied to the charge storage wells move the packet charges down the parallel-column shift registers (C1-C6) at a rate substantially equal to the scanning rate of the scanner thereby providing time delay with integration of the charge packets before the signal leaves the infrared sinsing charge transfer device matrix. To provide charge storage wells of sufficient depth to hold the integrated charge packets the pulses applied to each succeeding stage potential well electrodes or groups of electrodes are increased in voltage. The charge packets from the parallel-colum registers (C1-C6) are clocked out by a serial shift register (46) to a floating gate or diode where the charge packet creates a voltage signal for signal processing by the signal processor. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0131880-A2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0131880-A3 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2207020-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-4952809-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2207020-A |
| priorityDate | 1981-06-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.