| abstract |
As is known, two-transistor memory cells of this type have a memory transistor and a switching transistor, the switching transistor being designed as a normal MOS transistor. The memory transistor, on the other hand, has a floating gate and a control gate, the floating gate being located both above the channel region and above the erase region in the part of the silicon crystal allocated to the memory cell. It is now desirable that the oxide layer carrying the floating gate is set thicker at the channel region of the memory transistor than at the erase region in a defined manner and that the oxide layer at the erase region also has a defined thickness.n n n For this purpose, according to the invention, the oxide serving as a base for the floating gate of the memory transistor is produced in two steps by oxidation of the silicon surface. Immediately after the first oxidation process, the oxide formed is removed from the surface of the extinguishing area, while it remains in the channel area. In a second oxidation process that follows, the silicon surface in the quenching area is oxidized again and the oxide at the channel area is brought to its final strength. Finally, a layer consisting of doped polysilicon is deposited on the two parts of the oxide layer and the floating gate is formed therefrom, so that it is located both above the channel region and above the erasure region of the silicon surface. |