http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-0020470-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-2051 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-8015 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-527 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-80 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-38 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-20 |
| filingDate | 1980-04-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1984-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 1984-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | EP-0020470-B1 |
| titleOfInvention | Modular processor system |
| abstract | A signal processing system that has an improved modular architecture so that a selected number of arithmetic element (AE) units may be utilized with a single arithmetic element controller (AEC) unit to provide a system that can be readily expanded or decreased on computational ability. All of the AE units perform similar calculations under control of the AEC unit in response to common address control and coefficient signals. Each AE units has its own extended work store (EWS) unit with all of the EWS units responding to the same address and control signals, from either the AEC unit or an external interface unit to conform to the modular architecture. Each EWS unit is synchronized with the AE unit, thus allowing continuous and high speed computations to be performed. Also, each of the EWS units is coupled to the external interface unit for receiving and transferring data when not being accessed by the AEC unit. The AE units, each of which are similar, may have a single multiplier and storage unit matched to a plurality of register and arithmetic logic (RALU) units so that parallel calculations may be performed utilizing the multiplier ouput data, thus increasing the overall speed of calculation a plurality of times of the system clock speed. Another feature of the invention is that the AEC unit has an architecture that allows simplified programming. The processor system also includes a control arrangement that allows, upon failure of an AE unit or EWS unit, a redundant AE unit and EWS unit to be utilized. |
| priorityDate | 1978-10-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.