http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-4438518-A1

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-34
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
filingDate 1994-10-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5dd8736ada4277c0cc521fc1a915808a
publicationDate 1995-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber DE-4438518-A1
titleOfInvention Semiconductor component with buried bit line and method for its production
abstract A buried bit line cell increases the integration density of a semiconductor device such as a DRAM. The semiconductor device includes: a semiconductor substrate (10) having a plurality of spaced apart first pillars (18) formed therein with isolated first trenches therebetween and second pillars (18a) connected to the first pillars (18) thereunder with isolated second trenches therebetween; a first insulating layer (33, Fig. 2 - not shown) formed inside the first trenches and isolated by a gate insulating layer (30, Fig. 2 - not shown) and gate electrode 31 enclosing the first pillars; impurity-doped regions having a first and second impurity-doped region (44, 43) vertically formed in the first and second pillars and a channel region therebetween; a bit line (27) formed in the bottom and on the sidewalls of the second trenches and connected to the impurity-doped regions; a second isolation insulating layer (28(28a), Fig. 2 not shown) formed in the bottom of the first trenches and inside the second trenches, for isolating the bit lines; and a word line (31) isolated by the first isolation insulating layer and connected to the gate electrode. Problems due to a deep trench and step formation are resolved by controlling the height of the first and second pillars (18, 18a) and the storage node (41) of a capacitor. <IMAGE>
priorityDate 1994-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

Predicate Subject
isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419579069

Total number of triples: 14.