http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-3231457-A1

Outgoing Links

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31138
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-027
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
filingDate 1982-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0408491dd00494057cc4ae70f7c6d7ab
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publicationDate 1984-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber DE-3231457-A1
titleOfInvention METHOD FOR GENERATING STRUCTURES FOR INTEGRATED SEMICONDUCTOR CIRCUITS BY REACTIVE ION NETWORKING
abstract The process of the invention uses as the mask (2) negative lacquer structures (2) produced by electron-beam writing, and, before the reactive ion etching of the structures (1,4) which, for example, serve as conductor patterns, an additional dry etching process is carried out for a short time in an oxygen atmosphere at low pressure and in the same parallel plate reactor in order to produce steep lacquer flanks (2). This provides the possibility of shortening the conductor structures (1,4) anisotropically, i.e. without undercutting. The process is applied in the metallisation of integrated circuits by electron-beam writing. <IMAGE>
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5171718-A
priorityDate 1982-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 25.