| abstract |
The method of making a monolithic integrated semiconductor device with vertical and lateral NPN, P-JFET, P-MOS, and D-MOS elements, includes forming these elements on the surface of a monocrystalline P conductive substrate by selectively forming an N + zone. An upper layer of n conductive semiconductor material on this zone at each point where a diffusion MOS element or a lateral NPN element is to be formed. Insulating PN transition zones are formed between P + zones, through the epitaxial layer. In the selected zones, a thin doped P-conductive surface is formed and another in the D-MOS regions. Further zones are formed for source and drain zones, and for the collector and emitter contacts. The gate insulators are selectively formed and the concentrating voltage for the P-MOS elements is applied. Boron ions are implanted to form the depletion channels for P-MOS and P-JFET elements and contacts and metallising are added. |