http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-19963502-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36f8253f3d0d59bcd9259217d4385d10 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1048 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4087 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-18 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-408 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-06 |
| filingDate | 1999-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b4714a70196e2efa4314b11a03b353ef http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aeb79ec1cf9cafe60600461ae2bc74f7 |
| publicationDate | 2001-07-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-19963502-A1 |
| titleOfInvention | Circuit arrangement for an integrated semiconductor memory with column access |
| abstract | A circuit arrangement for an integrated semiconductor memory has memory cells (MC) which are arranged in a matrix-shaped memory cell array (1) and are combined into addressable units of column lines (BL) and row lines (WL). A decoder (10) for selecting one of the column lines (BL) by means of a column selection signal (S11) has a connection (12) for an input signal (S12) for activating the column selection signal (S11). A line activation signal (S21) is used to activate a line access signal sequence (S22, S23). The connection (12) for the input signal (S12) of the decoder (10) is connected to a signal (S22) from the line access signal sequence (S22, S23) which indicates that the line access has been completed. Successive signals in the process of memory access prevent the column access from occurring before the end of the row access. The memory access is controlled in a self-adjusting manner. |
| priorityDate | 1999-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.