http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-19954845-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_526cb931f1382d6e016ee651d55e1365 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B53-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B53-30 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8246 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C14-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10 |
| filingDate | 1999-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_abe30d8c0a58966d0edb31c67281ee96 |
| publicationDate | 2000-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-19954845-A1 |
| titleOfInvention | NAND type non-volatile ferroelectric memory cell, method of manufacturing the same, and non-volatile ferroelectric memory using the same |
| abstract | A NAND type non-volatile ferroelectric memory cell and a non-volatile ferroelectric memory are provided with such cells in which the access numbers to main cells and reference cells are the same, respectively, in order to keep voltages induced in a bit line by the reference cells and the main cells constant in order to keep the Improve operational properties, minimize the layout area and achieve high integration density of components. DOLLAR A The memory cell is provided with the following: DOLLAR A - a number N of series-connected transistors; DOLLAR A - a bit line (B / L) to which an input terminal of a first transistor and an output terminal of an Nth transistor among the N transistors are connected; DOLLAR A - word lines (W / L) each connected to gates of the transistors with the exception of the Nth transistor; DOLLAR A - a signal line (WEC) connected to the gate of the N-th transistor and connected so that an activation signal is applied to it only in a write or in a re-store mode; and DOLLAR A -ferroelectric capacitors, each connected to both the word lines and the output terminals of the transistors. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2360153-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2360153-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-10003812-B4 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6477076-B2 |
| priorityDate | 1998-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.